Power MOSFET (metal-oxide-semiconductor field effect transistor) devices have many industrial applications, such as power amplifiers, power convertors, low noise amplifiers and digital Integrated Circuits (IC) to name a few. As a common element for a great variety of electronic products, the practitioners in the art of MOSFET device design and fabrication are constantly improving its performance parameters such as break down voltage Vbk, on-state resistance RD Son, device size and frequency response, to name a few.
FIG. A1 through FIG. A4 are excerpts from a prior art tutorial entitled “Superjunction devices & technologies—Benefits and Limitations of a revolutionary step in power electronics” by Dr. Gerald Deboy and Dr. Florin Udrea, published in EPE 2007—Aalborg, Denmark, 2-5 Sep. 2007. This tutorial dealt with an overview of the concept of employing superjunction devices to simultaneously improve Vbk and Rdson of a power MOSFET.
As originally invented at the beginning of 1980s, the drift region of a superjunction transistor device is formed of multiple, alternate n and p semiconductor stripes. Provided that the stripes are fairly narrow and the number of charge carriers within adjacent stripes are approximately equal, or so-called charge balanced, it is possible to deplete the stripes at relatively low voltages. Upon depletion, the stripes appear to be an ‘intrinsic’ layer and a near uniform electric field distribution is achieved, resulting in a high breakdown voltage. Both lateral superjunction devices (FIG. A1 and FIG. A2) and vertical superjunction devices (FIG. A3 and FIG. A4) can be manufactured using the superjunction concept. While the lateral devices tend to be more suitable for integration, the latter devices could be used for discrete devices. More specifically, FIG. A1 illustrates vertically stacked stripes in lateral configuration. FIG. A2 illustrates stripes arranged in the third dimension, called 3D Resurf in lateral configuration. FIG. A3 and FIG. A4 are arrangements suitable for vertical MOSFETs (Cool MOS, MDMesh). The most striking feature of all superjunction devices are their capability to break the limit line of silicon being imposed on conventional, non-superjunction devices. This limit is based on the need to serve with one degree of freedom namely the doping profile of the n-region the conflicting goals of high Vbk and low on-state-resistance. Superjunction devices add, due to their internal structure, a second degree of freedom namely the design and pitch of the additional p-columns. The former vertical electric field of the conventional, non-superjunction devices is therefore transformed into a three dimensional vectorial field with at least the theoretical capability to continuously reduce the RDSon by making the pitch of the p-columns smaller and smaller.
FIG. B1 through FIG. B3 illustrate numerous specific charge balanced stripe geometries and their method of making under additional prior arts. The method for making charge balanced vertical stripes of alternating conductivity types (p-type & n-type) of FIG. B1 is used by many companies. In this case, six (6) cycles each consists of an epitaxial growth and a multi-zone ion implantation are sequentially carried out atop a substrate (not shown here). Afterwards, a high temperature, long diffusion process is required to “expand” the multiple ion implantation zones to their final sizes. A typical diffusion process may require a temperature of 1150 degree C. for 6-10 hrs thus entailing an undesirable high thermal budget. In this illustrated example, cycle one epitaxial growth makes layer-1 1 and cycle one multi-zone ion implantation simultaneously makes implants 1a, 1b and 1c where layer-1 1 is of opposite conductivity type with respect to that of the implants 1a, 1b and 1c. For another example, cycle two epitaxial growth makes layer-2 2 and cycle two multi-zone ion implantation simultaneously makes implants 2a, 2b and 2c where layer-2 2 is of opposite conductivity type with respect to that of the implants 2a, 2b and 2c, etc. As a specific example, each of the epitaxial layers 1 through 6 is 5-7 micron in thickness and can be made of N− type while the implants 1a through 6c are made of P− type semiconductor material. In the end, the charge balanced vertical stripes correspond to column 10W, column 10A, column 10X, column 10B, column 10Y, column 10C and column 10Z. Another disadvantage of this method is, for charge balanced stripes of large height the number of cycles increases accordingly resulting in even slower production throughput and high cost of production.
The method for making charge balanced vertical stripes of alternating conductivity types (p-type & n-type) is shown FIG. B2. Here, a bulk semiconductor layer 20 can be epitaxially grown atop a substrate (not shown here). With photolithography and anisotropic etching numerous trenches 22a, 22b, 22c are made into the bulk semiconductor layer 20. Each trench has a trench depth D and trench width W with a corresponding aspect ratio A/R=D/W. The trenches 22a, 22b, 22c can then be filled up by epitaxially growing a fill semiconductor material 25 therein to fill in the entire deep trench, thus resulting in charge balanced columns 20W, 25A, 20X, 25B, 20Y, 25C and 20Z of alternating conductivity types. As a typical example, the substrate can be of N+ conductivity type, the bulk semiconductor layer 20 is N− of thickness 40-50 micron, trench width W is 4-6 micron while the fill semiconductor material 25 is P−. Consequently, the aspect ratio A/R can be very high (8-15) causing the appearance of numerous unfilled internal voids 26a, 26b, 26c in the fill semiconductor material 25. In turn, these internal voids can disturb charge balance and lead to undesirable low Vbk & high device leakage current.
FIG. B3 illustrates a third method for making charge balanced vertical stripes of alternating conductivity types disclosed by Hamza Yilmaz, et al. in U.S. application Ser. No. 12/319,164 filed Dec. 31, 2008. A bulk semiconductor layer 30 is epitaxially grown atop a highly doped bulk semiconductor layer 42. With photolithography and anisotropic etching a trench 32 is made into the bulk semiconductor layer 30. The trench 32 has a trench depth D and trench width W with a corresponding aspect ratio A/R=D/W. Nine (9) consecutive epitaxial layers of alternating, charge balanced conductivity types are grown on top forming layers 31a, 32b, 33a, 34b, 35a, 36b, 37a, 38b, 39a with a residual central space column. The central space column is then filled with the formation of a fill material 44 such as insulating oxide or intrinsic silicon whose charge balancing behavior is insensitive to any unfilled internal voids therein. A high temperature, long diffusion process is then carried out to propagate the dopants in the highly doped bulk semiconductor layer 42 into layers 31a-39a, hence dominating as a single conductivity type till a dopant diffusion front 48 (see bottom dashed line). Finally, a chemical mechanical polishing (CMP) process is carried out to remove the top horizontal portions of the layers 31a-39a and level the top surface (see top dashed line). As a typical example, the layers 31a-39a are each 1-2 micron thick. As before, the high temperature, long diffusion process entails an undesirable high thermal budget. In the end are left vertical charge balanced columns of alternating conductivity types.
In view of the above, there exists an ongoing need to improve the process of making high quality charge balanced drift region for superjunction semiconductor devices without incurring a high thermal budget and with higher production throughput.